1. Field of the Invention
The invention generally relates to the placement of fuses in a semiconductor floorplan. In particular, the invention provides a method for and an apparatus in which the FSOURCE connection is split into multiple nets, allowing more efficient placement of primary fuses in the floorplan and reliable programming thereof.
2. Background of the Invention
The advent of electronic fuses for connecting or disabling redundant structures in, for example, RAMs has introduced many new problems for the physical design of integrated circuits that use redundant structures to improve manufacturing yield. One such problem is the electrical constraints on the FSOURCE net. FSOURCE ports are the chip interface ports (e.g. wirebond pads, C4 pads, or the like) that supply the voltage necessary to blow each fuse in a fuse macro. While C4 pads are preferred and the terminology “C4 pads” is used hereinafter, it should be understood that any other interface port structure (such as wirebond pads) may be used. For example, in some integrated circuits, a fuse domain includes the following elements:
1. a single fuse controller to control all the fuse macros
2. up to 64 primary fuse macros for wafer level fuse blow
3. 4 secondary fuse macros for module level fuse blow
4. 2 tertiary fuse macros
5. a single FSOURCE IO that supplies current from a chip signal IO to all the fuse macros during fuse blow.
The wire associated with the FSOURCE is referred to as a “fatwire” (depicted as a relatively heavier connections in the Figures) because the type of wire used in an FSOURCE connection which has a width that can be over 100 times that of a minimum width wire in the circuit in order to carry sufficient current while limiting voltage drop per unit length during programming of fuses.
During manufacturing tests, only one fuse macro in a domain is blown at a time. In order to ensure sufficient voltage to blow a fuse inside a fuse macro, the point to point resistance between the fuse macro and the FSOURCE fatwire IO must be considered. For example, in some systems, this point to point resistance must be held to about 10 ohms. In order to meet this resistance constraint, even considering the cross sectional dimensions of the fatwire, the fuse macro must be located relatively close to the FSOURCE fatwire IO. For a full domain of 70 fuse macros (64 primary+4 secondary+2 tertiary), this means that all the fuse macros must cluster near the FSOURCE fatwire IO. This requirement can cause several floorplanning problems during physical layout of the chip because such a cluster of fuse domain blocks takes up a relatively large area on the chip, typically about 2 mm×2 mm of surface area. Associated problems include:
1. Fuses and their placement are not critical in terms of performance of the chip, yet they must cluster as a large composite block. This cluster can perturb the placement of more critical blocks resulting in a less than ideal floorplan.
2. This large cluster can block the area under signal C4 pads and leave no room for IO cells, for example, for loading signals on or off. Placing an IO cell too far away from its C4 pad will violate the resistance constraint on the connection between the IO cell and its C4 pad. This can render the signal C4 pad unusable. Thus, it is desirable to spread out the fuse macros instead of clustering them.
The prior art has thus far failed to provide a solution to the problems associated with efficient placement of fuse macros on the floorplan of a semiconductor chip.